求帮写VHDL，将50mhz分频6个频率，驱动蜂鸣器，产生6种不同声音

Question

求帮写VHDL，将50mhz分频6个频率，驱动蜂鸣器，产生6种不同声音

Answer 1

--一顿早饭的时间写的，综合仿真均已通过，放分吧~
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity MusicBox is port
(
clk:in std_logic;--主频 可设置成50M
rst:in std_logic;--复位信号 低有效
selectin:in std_logic_vector(5 downto 0);--频率选择输入，因为只有一个输出，所以必须得有选择
final:out std_logic--频率输出
);
end entity;
architecture behav of MusicBox is
signal freqout:std_logic;
signal freq:std_logic_vector(16 downto 0);
signal cnt:std_logic_vector(16 downto 0);
constant do:std_logic_vector(16 downto 0):="10111110101111000";--do的频率256Hz，50M/256Hz≈195312再除以2是方波翻转周期97656，二进制10111110101111000
constant re:std_logic_vector(16 downto 0):="10101001100010101";--re的频率288Hz，计算同上
constant mi:std_logic_vector(16 downto 0):="10011000100101101";--mi的频率320Hz，计算同上
constant fa:std_logic_vector(16 downto 0):="10001110110001011";--fa的频率342Hz，计算同上
constant so:std_logic_vector(16 downto 0):="01111111001010000";--so的频率384Hz，计算同上
constant la:std_logic_vector(16 downto 0):="01110010100111101";--la的频率426Hz，计算同上
begin
final <= freqout;
process(clk,rst)
begin
if rst = '1' then
if rising_edge(clk) then
case selectin is
when "000001" => freq <= do;
when "000010" => freq <= re;
when "000100" => freq <= mi;
when "001000" => freq <= fa;
when "010000" => freq <= so;
when "100000" => freq <= la;
when others => freq <= "00000000000000000";
end case;
if freq = "00000000000000000" then--没有输入则不响
freqout <= '0';--假设输出低则蜂鸣器不响
else
if cnt = freq then--计数器
cnt <= "00000000000000000";
freqout <= not freqout;--输出取反<=>输出方波
else
cnt <= cnt + 1;
end if;
end if;
end if;
else --复位信号有效时
freqout <= '0';
freq <= "00000000000000000";
cnt <= "00000000000000000";
end if;
end process;
end architecture;