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英语翻译1.ASICF/EEngineer-可操作LogicSimylator(NC-venlog,ModelSim等)-DTF设计经历者优先-可操作SynopsysSW优先(Designcompiler,DTFcompiler,Primetime,Teramax等)2.ASICLayoutEngineer-AutoP&RLayout经历者-可操
题目详情
英语翻译
1.ASIC F/E Engineer
-可操作 Logic Simylator(NC-venlog,Model Sim等)
- DTF 设计经历者优先
- 可操作Synopsys SW优先
( Design compiler,DTF compiler,Primetime,Teramax等)
2.ASIC Layout Engineer
- Auto P&R Layout 经历者
- 可操作Synopsys SW 优先
( IC compiler,Astro,SoC Encounter,Calibre,Hercules等 )
- Verification 经历者优先
3.SoC 设计
- RTL Coding及 System Level integration
- ARM Based SoC 开发经历者优先
英语翻译成汉语.
1.ASIC F/E Engineer
-可操作 Logic Simylator(NC-venlog,Model Sim等)
- DTF 设计经历者优先
- 可操作Synopsys SW优先
( Design compiler,DTF compiler,Primetime,Teramax等)
2.ASIC Layout Engineer
- Auto P&R Layout 经历者
- 可操作Synopsys SW 优先
( IC compiler,Astro,SoC Encounter,Calibre,Hercules等 )
- Verification 经历者优先
3.SoC 设计
- RTL Coding及 System Level integration
- ARM Based SoC 开发经历者优先
英语翻译成汉语.
▼优质解答
答案和解析
1. ASIC F/E Engineer
--Be able to operate Logic Simylator(NC-venlog, Model Sim etc.)
--DTF designing experiences is preferred
--Being able to operate Synopsys SW is preferred
( Design compiler, DTF compiler, Primetime, Teramax etc.)
2. ASIC Layout Engineer
- Auto P&R Layout experiences
- Being able to operate Synopsys SW is preferred
( IC compiler, Astro, SoC Encounter, Calibre, Hercules etc. )
- Verification experiences is preferred
3. SoC designing
- RTL Coding and System Level integration
- ARM Based SoC developing experiences is preferred
--Be able to operate Logic Simylator(NC-venlog, Model Sim etc.)
--DTF designing experiences is preferred
--Being able to operate Synopsys SW is preferred
( Design compiler, DTF compiler, Primetime, Teramax etc.)
2. ASIC Layout Engineer
- Auto P&R Layout experiences
- Being able to operate Synopsys SW is preferred
( IC compiler, Astro, SoC Encounter, Calibre, Hercules etc. )
- Verification experiences is preferred
3. SoC designing
- RTL Coding and System Level integration
- ARM Based SoC developing experiences is preferred
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